Robust Elmore Delay Models Suitable for Full Chip Timing Veri cation of a 600MHz CMOS Microprocessor

In this paper we introduce a method for computing the Elmore delay of MOS circuits which relies on a model of the capacitance of MOS devices and a model of the Elmore delay of individual MOS devices. The resistance of a device is not explicitly modelled. The Elmore models are used to compute the Elmore delay and the 50% point delay of CMOS circuits in a static timing veri er. Elmore delays computed with these models fall within 10% of SPICE and can be computed thousands of times faster than if computed using SPICE. These models were used to verify critical paths during the design of a 600MHz microprocessor.